Online course that explains all the components in a System Verilog testbench and how they work together in fully verifying a Design Under Test. For a given Design description, the course explains how to arrive at a test plan, test bench architecture, and write a complete System Verilog testbench from scratch.
Prerequisites
Good understanding of all constructs in System Verilog
Basic knowledge about a Chip
What will I learn
Verification approach and methodology in the industry